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Genericity of VHDL descriptions

Through this article we want to describe two configurable components:

  • a multi-function operator, structurally described from an elementary cell
  • a FIFO that allows the communication of messages between two asynchronous processors.

 

1. Arithmetic operator

 

We want to implement an arithmetic operator with the following structure:

ffd4acd1f30f881a7d08dd4a5278d8329124faea4ccb1b96d6b857030dd2369a.png

 

We want this operator to be able to perform the following main operations:

  • the transfer of the operand A
  • the increment
  • the addition of the two operands
  • the addition with increment
  • the addition of the operand A with the complement to 1 from B
  • the subtraction B from A
  • the decrementation of A by 1.

 

This has been represented according to the following functional table:

444900a9fcd1b3d451e90d56af7fe3ba1c94c34f5dae86739f69b6300d73026d.png

 

We describe the elementary cell of the arithmetic operator from an entity-architecture pair as follows:

270bebc5839ddd2922a6c541a8119cbd6ce200788404c47bfe06b58cd3fdec20.png

7cddb85c5faef9a8384aff077da9ab4b363e344650ab6c050a73d7230c5b5ae2.png

 

We describe the following test bench to allow us to validate our operator on the operations stated previously.

We obtain the following simulation:

ef1fd69c1a69d6bd78e8ca4c55418bfbe4a1a53b8a76b562ed64617debd10c31.png

 

The result displayed on G corresponds well to our previous functional table.

 

2. The FIFO component

 

We wish to describe a data storage circuit of FIFO (First in, First out) type represented as follows:

6f7a940445e77614da5563dc96c4a48f44bb9d15ed66495e56ba03cce1bca1b1.png

 

  • Datain: data entry to write to the FIFO
  • Dataout: value of the oldest unread value in the queue
  • R / W: represents the type of operation to be performed on the queue
  • enable: to authorize the operation
  • full: status indicator indicating whether the queue is full
  • empty: status indicator indicating whether the queue is empty

 

We thus seek to describe the following block diagram:

409c208da92843a48fba5f373cb4f54f79495785d65f21d10ea4af6edd4e6910.png

 

We define the previous entity/architecture pair making it possible to describe the FIFO using concurrent instructions. We obtain the following chronogram:

258a1b9c7ac31140b703e60459930c0e129493d992bcd0e72b088f180bf02d72.png

 

 

Through this article we described two configurable components:

  • a multi-function operator, structurally described from an elementary cell
  • a FIFO that allows the communication of messages between two asynchronous processors.

 

This article is part of my Electronics posts blog, in which you can find few articles about things i learnt in my post-graduated school :)

 

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